PARTNO    Applix_1617_ZPAL1_V8;
                NAME      Applix_1617_ZPAL1_V8;
                DATE      2023-11-01;
                REV       01 ;
                DESIGNER   ;

/*
2023-11-01 First draft guess at what is going on, 
	from looking at the circuit and the manual.
	Not tested yet!!!
*/

device g16V8;	/* modern replacement for 16L8 */

pin 1 = MAP;	/* Not used at present*/
pin 2 = BANK;	/* from control latch */
pin 3 = A15;	/* from CPU */
pin 4 = A7;	/* from CPU */
pin 5 = A6;	/* from CPU */
pin 6 = A5;	/* from CPU */
pin 7 = A14;	/* from CPU */
pin 8 = A13;	/* from CPU */
pin 9 = /MREQ;	/* from CPU */

pin 10 = GND;	/* */

pin 11 = /IORQ;	/* from CPU */
pin 12 = /IOEN;	/* to LS138 decoder */
pin 13 = /WAIT;	/* to IC6 pin 2 */
pin 14 = /SRAM1SEL;	/* */
pin 15 = /SRAM0SEL;	/* */
pin 16 = /ROMSEL;	/* */
pin 17 = /FDCCS;	/* */
pin 18 = /SCCCS;	/* */
pin 19 = /SCISCS;	/* */

pin 20 = VCC;	/* */


/*

The Z80’s I/O port address map

Address	Name		Function

00H	PORT		Read only input port.
08H	LATCH		Read/write disk select latch
10H	ZINTS		Write: interrupt the 1616.
10H	ZCLRINT		Read: clear pending Z80 interrupt.
18H	SDATA		Read/write 1616 communications port.

20H	SCSIBASE	SCSI controller base address

40H	FDCBASE		Floppy disk controller base address.

60H	SCCBASE		Serial communications controller base address.
*/

IO_BLOCK_00H	= IORQ & /A7 & /A6 & /A5 ;
IO_BLOCK_20H	= IORQ & /A7 & /A6 &  A5 ;
IO_BLOCK_40H	= IORQ & /A7 &  A6 & /A5 ;
IO_BLOCK_60H	= IORQ & /A7 &  A6 &  A5 ;

/* Pins */

IOEN		=	IO_BLOCK_00H;	/* */
SCISCS		=	IO_BLOCK_20H;	/* */
FDCCS		=	IO_BLOCK_40H;	/* */
SCCCS		=	IO_BLOCK_60H;	/* */

/*
	Z80 MEMORY MAP

	0000H-5FFF H:ROM
	6000H-7FFF Common RAM bank H:
	8000H-FFFF Switching RAM bank H:
*/

ROMSEL		= MREQ & /A15 & /A14 		/* 0000-3FFF */
		+ MREQ & /A15 &	 A14 & /A13;	/* 4000-5FFF */

SRAM0SEL	= MREQ & /A15 &	 A14 &  A13	/* 6000-7FFF = 8K */
		+ MREQ &  A15 & /BANK	;	/* 8000-FFFF = 32K */

SRAM1SEL	= MREQ &  A15 &  BANK 	;	/* 8000-FFFF = 32K */

/*
At present all I/O transactions and ROM reads have a wait state. 
RAM reads and writes proceed at full speed.
*/

WAIT		= IORQ
		+ ROMSEL ;